1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which the area occupied by a data bus made of data line pairs is reduced, so that the chip area can be decreased.
2. Description of the Related Art
One of semiconductor integrated circuits is described in Japanese Patent Application Kokai (Laid-open Publication) No. 2001-344976.
The semiconductor integrated circuit of Japanese Patent Application Kokai No. 2001-344976 has a plurality of banks and a plurality of I/O circuits. The banks include a plurality of memory cells and can write data to and read from the memory cells. Each I/O circuit includes pads, input/output (hereafter “I/O”) buffers, and an I/O interface circuit. The banks are connected to the data bus, and the I/O circuits are also connected to the data bus.
In this semiconductor integrated circuit, data read from one or more memory cells in a certain bank is output to the data bus and transmitted on the data bus. Data transmitted on the data bus is captured by a certain I/O circuit and output to an external circuit or device. Data input from a certain I/O circuit is input to the data bus, is transmitted on the data bus, and is written to one or more memory cells within a certain bank.
In the semiconductor integrated circuit of the above mentioned Japanese Patent Application Kokai, I/O data processed by the bank(s) and I/O circuit(s) are exchanged through the data bus which extends long within the chip. The long data bus is provided within the chip according to the I/O data bus length of the product specification.
If the data bus has a considerable length in the chip, countermeasures, such as the insertion of shielded lines and the positioning of circuits which may become noise sources in positions other than below the wiring layer of the data bus, must be adopted in order to avoid the influence of crosstalk (signal leakage) between the data bus, other neighboring wiring, and circuits below the data bus. Hence as the amount of data transmitted is increased and the number of lines of the data bus increases, the chip area increases.